Embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a memory device having a latency control circuit configured to generate a latency signal activating on an input circuit and an output circuit, at a time point based on a clock signal.
In a dynamic random access memory (DRAM), a command may be typically input in synchronization with a clock signal CLK, and data may be typically input and output in synchronization with a data strobe signal DQS. When a write command is applied to the DRAM, a write signal may be generated based on the clock signal CLK, and provided to a data input circuit as a write latency signal for latching write data after a write latency WL indicated by a multiple of a clock cycle. The data input circuit may receive write data based on the data strobe signal DQS, align and latch the write data in response to the write latency signal, and transmit the latched write data to a memory cell array of the DRAM.
The write data input based on the data strobe signal DQS and the write latency signal generated based on the clock signal CLK may be provided in different domain regions. In semiconductor devices of the different domain regions, delay times may vary due to differences in characteristics between the semiconductor devices, which are caused by process variation and temperature (PVT). Thus, a setup alignment margin or hold alignment margin between the write latency signal and the write data may be deficient, thereby resulting in occurrence of missing data.